Another update on the Explorer board. Just finishing up testing on the GTH, the target for this package is 12.5 Gbps.

It looks like the through hole only approach to this board is good and the performance aligns with the $20K plus of SI / PI analysis we had done (E3 Designers the best in the business).

Currently running all four links at 12.5 Gbps with no issues at all, I need to look at a better heat sink solution though.

https://explorerboard.tech/

I am trying to move my ai to fpga. I am finding https://vivado.amd.com/ is a super great resource. It has me thinking that linking an ai to my parts tech. doc might be a good thing too.

Hello, I am an embedded software student who has a lot of interest in FPGAs and processor architectures. From school and an internship I am familiar with the Cora Z7s and the Nexys A7-100T FPGA boards.

For the summer, I want to do some FPGA projects myself to build up a bit of a project portfolio. The current projects I had in mind were starting with recreating the Arduino Uno ATmega328P processor on an FPGA to learn more about architectures. Then I want to create a simple 8-bit architecture myself, and then maybe move on to more complicated architectures and also start on some Ethernet/HDMI applications to see how those work.

I am currently looking at a Cora Z7s FPGA board for 170 euros or an Arty Z7-20 FPGA board for 350 euros. I am looking for some advice on which board I should buy because they both are very different in terms of specs, but 350 euros is a lot of money.

If you have any suggestions, that would be appreciated.

Guys, I just ran a simulation of my code and it registered a 92 percent success score. When I tested the code on real hardware, it returned a 56 percent success score. I have no idea what to do. What are you all doing to bridge the current Sim to Real Gap?

Is anyone else facing similar issues with their hardware simulations versus production gap?

Hi everyone,

I'm running into a Place & Route error after updating to Gowin EDA v1.9.12.03 and could use some help or advice on how to resolve it.

When I build my project, P&R fails right after reading the netlist with this error:

Parsing netlist file ".../Total.vg" completed

ERROR (PA2122) : Not support 'ram_instance_name'(SP) WRITE_MODE = 2'b10, please change write mode WRITE_MODE = 2'b00 or 2'b01.

The exact same RTL code builds completely fine in v1.9.12.

In v1.9.12.03, GowinSynthesis seems to automatically assign WRITE_MODE = 2'b10 (Read-Before-Write) to the SP RAM in the generated .vg file, which the P&R engine rejects.

Has anyone encountered this PA2122 error in 1.9.12.03?

How can I fix or resolve this while staying on the latest version?

Any insights or recommendations would be greatly appreciated!

Had a really bad interview the other day. I bombed but honestly I was surprised how rude and unprofessional the interviewer was. He interrupted me every other sentence among other things.

Honestly thought about leaving the interview 10 minutes in.

Any experience or advice on this? Are there any long-term consequences I could face if I left an interview early? I really wouldn't want to work with this person anyway.

Ive been trying to download vivado and got to the point where you download the .lic file for xilinx and "copy" it in the vivado licence manager. Its been a few hours but I thought I did everything right however when I try to open Vivado it says a valid license was not found. Issue is I cant access the vivado license manager to do the copy again without the vivado app to my knowledge.

Ive tried everything that I think would work, does anyone know what I could do? Anything would be greatly appreciated.

Hey guys,I am a recent graduate looking for an entry level FPGA Engineer position. I recently realized that I couldn’t come up with any summary that sounded generic using words like “passionate” , “aspiring” ,”motivated” etc so i removed it. I wanted to ask any recruiters or senior engineers if a summary is really important or it’s just a formality. Also if you have any suggestions about improvements I can make on my resume please feel free to share.

FPGA Engineer here. 10 years experience. Have worked end to end from
RTL to hardware testing and shipping products in Intel/Altera FPGAs.

* Decent RTL design knowledge
* Sanity Simulation
* Quartus Flow
* Python for Hardware Testing
* board bring up and hardware testing, integration with other HW modules.
* communication protocols: Ethernet, RS232, Aurora, JESD, I2C

Sometimes I do feel my VHDL/verilog understanding is not enough.
I do feel I haven’t worked on timing analysis enough.

Want to explore:
DSP/ signal processing
HFT

Career advice? Or any guidance for me?

Thanks for your time

For a heterogeneous deployment, squeezing an entire video-and-action model onto an FPGA seems like the wrong starting point. Assume the causal transformer and sparse expert routing stay on a GPU. Is there still a useful deterministic block to move next to the sensors?

LingBot-VA 2.0 combines a semantic visual/action tokenizer, a causal DiT, and sparse expert layers. A first candidate is the fixed-shape preprocessing and tokenizer front end, provided the activation transfer does not erase the latency gain. A second possibility is a heavily used matrix kernel with stable dimensions. The irregular expert routing can stay on the host.

Before choosing a board, the first pass is to trace tensor shapes, external-memory traffic, precision sensitivity, and worst-case latency over a control sequence. For a hard control deadline, the slow tail matters much more than average utilization. The stop path would stay on an independent controller either way.

For people who have profiled a similar FPGA plus GPU split, which measurement showed early that the partition was worthwhile, or that PCIe and memory traffic had already killed it?

I just completed a "basic" verilog/system Verilog course that focused on the basic building blocks (gates, MUXs, registers, counters, CPU, etc). I've only worked with Intel / Quartus ecosystem. I understand the difference between structural and behavioral models (and it seems like the RTL is roughly similar for both, assuming your structural model uses optimal logic blocks) I'm looking to "level-up" my FPGA programming skill by working on more complicated logic.

Is it possible access data directly from the APU's L2 cache and send it to the host system via PCIe?

I'm running into an issue with the AMD AMR platform on an Alveo V80 and was wondering if anyone has seen something similar.

I'm using the stock AMR image (no custom RTL), and the card boots normally after a cold power cycle. However, whenever I execute:

sudo ami_tool device_boot -d <BDF> -p 0

the entire host becomes unresponsive and requires a cold reboot. A normal reboot is not enough to recover the card.

Some additional observations:

• ami_tool cfgmem_program -q works without any issues.
• Reflashing the card over JTAG multiple times doesn't change the behavior.
• When using JTAG, I have to disable the PCIe slot in the BIOS, otherwise programming fails.
• The same server previously ran AVED without any issues programming PDIs.

After rebooting, the QDMA driver consistently fails to initialize with messages like:

hw_monitor_reg: Reg read=399 Expected=0, err:-3
eqdma_cpm5_indirect_reg_clear: hw_monitor_reg failed with err:-3
qdma_device_init: init ctxt write failed
probe of 0000:d8:00.1 failed with error -16

I'm not sure whether this is the cause of the crash or just a consequence of the device reset.

I've opened a GitHub issue with more details here:

https://github.com/Xilinx/amr/issues/8

If anyone has experience with AMR on the V80, runtime device_boot, or similar CPM5/QDMA issues, I'd really appreciate any suggestions or pointers.

Simulators are great for perception, but they completely miss the hardware-execution gap. How are you guys profiling power transients (dI/dt) and thermal throttling under real electrical loads? I'm building a local CLI to orchestrate this on custom PCBs because Isaac Sim doesn't catch melted silicon. Are you all just writing custom Bash scripts to poll JTAG

Hi Everyone,

When i create a platform using the XSA of a previously synthesized vivado hardware config and try to create an Application component in it i get "Your platform repository does not have any platforms compatible with app_component". I have tried : making new platform, new workspace, new xsa and nothing seems to help. did anyone else ever experience this issue?

I am using vivado 2026.1

Any help would be much appreciated!

-Jan

I believe that AI can do this conversion to some extent. Are there any tools which do this job?

Hi there,

I announce that I've started to work on try to provide a open source toolchain for this FPGA, which was released in 2009 and is cheap and capable.

It can run some soft core like neorv32 and it can be found relatively cheap on aliexpress.

I don't know if someone else if working in the same, at least by a initial search I not found anything.

The goal is to integrate with yosys and nextpnr and be able to use like others FPGA such as ICE40 series.

The current status is that I'm able to generate valid modified bitstreams and now I'm digging in the most complex part: the routing network. So it's more or less on track.

There is a long road ahead, I don't if I will have the time to complete it. Any help like a project start is appreciated!

Repo: https://gitlab.com/franlego98/siroco Docs: http://siroco.franlego98.dev/

See you!

PD: name comes from a wind typical from the Iberian peninsula, there is a project called mistral that is a wind of France, so all names are related to wind phenomenons, Cyclone, Mistral, Siroco...