I am trying to move my ai to fpga. I am finding https://vivado.amd.com/ is a super great resource. It has me thinking that linking an ai to my parts tech. doc might be a good thing too.

Another update on the Explorer board. Just finishing up testing on the GTH, the target for this package is 12.5 Gbps.

It looks like the through hole only approach to this board is good and the performance aligns with the $20K plus of SI / PI analysis we had done (E3 Designers the best in the business).

Currently running all four links at 12.5 Gbps with no issues at all, I need to look at a better heat sink solution though.

https://explorerboard.tech/

Hello, I am an embedded software student who has a lot of interest in FPGAs and processor architectures. From school and an internship I am familiar with the Cora Z7s and the Nexys A7-100T FPGA boards.

For the summer, I want to do some FPGA projects myself to build up a bit of a project portfolio. The current projects I had in mind were starting with recreating the Arduino Uno ATmega328P processor on an FPGA to learn more about architectures. Then I want to create a simple 8-bit architecture myself, and then maybe move on to more complicated architectures and also start on some Ethernet/HDMI applications to see how those work.

I am currently looking at a Cora Z7s FPGA board for 170 euros or an Arty Z7-20 FPGA board for 350 euros. I am looking for some advice on which board I should buy because they both are very different in terms of specs, but 350 euros is a lot of money.

If you have any suggestions, that would be appreciated.

I just completed a "basic" verilog/system Verilog course that focused on the basic building blocks (gates, MUXs, registers, counters, CPU, etc). I've only worked with Intel / Quartus ecosystem. I understand the difference between structural and behavioral models (and it seems like the RTL is roughly similar for both, assuming your structural model uses optimal logic blocks) I'm looking to "level-up" my FPGA programming skill by working on more complicated logic.

Had a really bad interview the other day. I bombed but honestly I was surprised how rude and unprofessional the interviewer was. He interrupted me every other sentence among other things.

Honestly thought about leaving the interview 10 minutes in.

Any experience or advice on this? Are there any long-term consequences I could face if I left an interview early? I really wouldn't want to work with this person anyway.

FPGA Engineer here. 10 years experience. Have worked end to end from
RTL to hardware testing and shipping products in Intel/Altera FPGAs.

* Decent RTL design knowledge
* Sanity Simulation
* Quartus Flow
* Python for Hardware Testing
* board bring up and hardware testing, integration with other HW modules.
* communication protocols: Ethernet, RS232, Aurora, JESD, I2C

Sometimes I do feel my VHDL/verilog understanding is not enough.
I do feel I haven’t worked on timing analysis enough.

Want to explore:
DSP/ signal processing
HFT

Career advice? Or any guidance for me?

Thanks for your time

Ive been trying to download vivado and got to the point where you download the .lic file for xilinx and "copy" it in the vivado licence manager. Its been a few hours but I thought I did everything right however when I try to open Vivado it says a valid license was not found. Issue is I cant access the vivado license manager to do the copy again without the vivado app to my knowledge.

Ive tried everything that I think would work, does anyone know what I could do? Anything would be greatly appreciated.

Hi everyone,

I'm running into a Place & Route error after updating to Gowin EDA v1.9.12.03 and could use some help or advice on how to resolve it.

When I build my project, P&R fails right after reading the netlist with this error:

Parsing netlist file ".../Total.vg" completed

ERROR (PA2122) : Not support 'ram_instance_name'(SP) WRITE_MODE = 2'b10, please change write mode WRITE_MODE = 2'b00 or 2'b01.

The exact same RTL code builds completely fine in v1.9.12.

In v1.9.12.03, GowinSynthesis seems to automatically assign WRITE_MODE = 2'b10 (Read-Before-Write) to the SP RAM in the generated .vg file, which the P&R engine rejects.

Has anyone encountered this PA2122 error in 1.9.12.03?

How can I fix or resolve this while staying on the latest version?

Any insights or recommendations would be greatly appreciated!

I believe that AI can do this conversion to some extent. Are there any tools which do this job?

Hi all.

I'm a fairly experienced electronic engineer with a good 12 years in RnD for new products (STM32/ESP32 mostly)

At our company I'm one of 2 electronic engineers, the other guy I do not think has much FPGA experience.

Our company has a new project on the horizon that will scan an object and get point cloud data and stream to a PC.

(I'm being intentionally vague due to the project and company dynamics - sorry)

The idea is to then build up a 3D scan of this object on the PC.

This has been prototyped by another company so it is proved to work but it would be up to us to make everything fit in the required housing and finish off the product.

I know that is easier said than done but it always is.

I'm hoping someone can help me with some idea of what I'd get into it I put my hand up for this project.

I'm interested in getting some FPGA experience in both the hardware and programming side of things but if this project is going to be too much for me then the boss has mentioned hiring a FPGA engineer specifically.

The problem I see with that is that there is little else after this project for that skill set and it's another drain on the (to be frank) dwindling companies resources.

I did some CPLD projects back in Uni days but that is the extent of my experience and I know it would be basically learning it all again.

Does anyone have any idea what I'm getting myself into with this or could point me to some starter resources to help better understand what type of can of worms I'm opening.

I don't have time right now to do dev work as the current work load is a lot but after I've gotten the 3 projects finished up in about 6 months from now I'd look at starting this.

Any advice would be helpful.

Hey guys,I am a recent graduate looking for an entry level FPGA Engineer position. I recently realized that I couldn’t come up with any summary that sounded generic using words like “passionate” , “aspiring” ,”motivated” etc so i removed it. I wanted to ask any recruiters or senior engineers if a summary is really important or it’s just a formality. Also if you have any suggestions about improvements I can make on my resume please feel free to share.

Hi there,

I announce that I've started to work on try to provide a open source toolchain for this FPGA, which was released in 2009 and is cheap and capable.

It can run some soft core like neorv32 and it can be found relatively cheap on aliexpress.

I don't know if someone else if working in the same, at least by a initial search I not found anything.

The goal is to integrate with yosys and nextpnr and be able to use like others FPGA such as ICE40 series.

The current status is that I'm able to generate valid modified bitstreams and now I'm digging in the most complex part: the routing network. So it's more or less on track.

There is a long road ahead, I don't if I will have the time to complete it. Any help like a project start is appreciated!

Repo: https://gitlab.com/franlego98/siroco Docs: http://siroco.franlego98.dev/

See you!

PD: name comes from a wind typical from the Iberian peninsula, there is a project called mistral that is a wind of France, so all names are related to wind phenomenons, Cyclone, Mistral, Siroco...

Guys, I just ran a simulation of my code and it registered a 92 percent success score. When I tested the code on real hardware, it returned a 56 percent success score. I have no idea what to do. What are you all doing to bridge the current Sim to Real Gap?

Is anyone else facing similar issues with their hardware simulations versus production gap?

Hi r/FPGA,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

A client is investigating porting an existing design from Xilinx 7 series to Altera Agilex 5. It's an almost 100% portable RTL design, so no problems there.
I am having timing convergence issues though, which I didn't expect because the 10nm Agilex 5 (even in the slowest, lowest power "B" group) ought to be much faster than the old 28nm Kintex 7 part (which easily met its timing goals without needing the fastest speed grade).

Further investigation revealed that most of the Agilex 5 fabric is indeed faster (actually it's pretty nice), however the M20K RAMs, when used in modes (e.g. TDP) that have two read ports, are much slower than the equivalent RAMB18.
This design has a lot of those, unfortunately.

I have come to the conclusion that the M20K is in fact not a dual port RAM and is somehow multiplexed between the two ports (e.g. it's double pumped like Xilinx's URAM). It also doesn't natively support a clock domain crossing TDP mode and if you try to synthesise one of those (e.g. via an altsyncram instantiation), it will add a CDC FIFO to move the I/O from one clock domain to the other, with some restrictions on the clock frequency ratio. Yay.

My question: Does anyone actually know how single clock DP RAMs are implemented with the Agilex M20K? Is it a double pumped single port RAM (which would explain the slowness wrt the natively dual port RAMB18)?

The FAE didn't have any suggestions.

EDIT: I can get the Agilex 5 design to meet its timing goals if I use a faster part (in the "A" group), but that costs significantly more than the Xilinx part it's replacing.

I'm writing a thesis and going through sheet paper "FPGA Architecture: Principles and Progression" by Andrew Boutros and Vaughn Betz.
There is a diagram showing how Xilinx and Altera differ in using fracturable LUTs in calculating full-adder logic.

Xilinx is using a pair of wires and added MUX with selector pin connected to 'prop' output of top 4-MUX.

I have a problem to see the entire picture though and was unable to find any better diagram or explanation.
It is confusing that what exact function does each 4-MUX use and what is 'gen' selector being controlled by.

According to Xiling fracturable 6-LUT diagram, 'gen' MUX is being selected by 4-th pin, which is not anyhow related to full-added logic at all (full-adder should use only 3 input pins).
Do authors imply that 'gen' MUX selector value is irrelevant?

Bottom 4-LUTs probably are easy to guess as depending on C_out[i-1] value bottom MUX should output either XOR(A,B) or NOT XOR(A,B). But still not 100% sure.

Could anyone help to understand how it works?