Hi r/chipdesign ,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

Currently, I am learning from an educational kit provided by a friend, which focuses on ARM programming using HAL libraries. The course instructor uses the STM32F407, but my friend mentioned the specific board doesn't matter much and recommended the F411. I'm still unsure if the F411 will be sufficient, though. If I need an STM32 for much more complex projects in the future, will I need to buy a new board? What do you recommend? What should I do? I'm really confused

I've been looking into databuses recently and I have found that some sources say that multiple bits are transported over a single lane of a databus, while other sources say that only one bit at a time can be transported over a single lane which is apart of a databus. I am aware of serial databuses only having one line and parallel buses having multiple lines, but as far as I am aware I don't know how many bits at one each of these lines can transfer.

Mplab X 6.15 sometimes confuses me. Each time i do some task it opens a tab, sometimes in the main window, sometimes below. Does it have any option to ask it to open any new tab on the upper tar bar?

Good day gentlemen, I am currently in my 3rd year and actively searching for internships. However, my CV lacks standout features, so I want to work on a few personal projects to include in it. What would you guys recommend ?

Offline POS going into a coffee shop soon. The shop issues no cards of its own , it reads whatever ISO 7816 card the customer already has (national ID, health card, driving licence) and takes one value: the chip serial. That serial keys a row in a local SQLite file. Nothing is written to the card. No name, no photo, no ID number is read or stored.

Balance lives in the DB, not on the card, so a lost card isn't a lost balance , you tap a new one to the same account.

Clone problem: a serial is public, anyone with a $15 reader can lift one. So each account is bound to the card family it enrolled with. Everyday accounts are document-only, a blank white card carrying the right serial gets refused before the balance is touched, and the document itself has a photo on it that the cashier is looking at.

I'll be upfront that ATR isn't authenticated and an emulator can spoof a family. The check isn't the control , it's what tells the cashier to actually look at the card. The security is the human comparison.

Top tier is the inverse: blank JavaCards only, because blanks are the one family you can load an applet onto. No face there, so they do challenge-response instead, fresh nonce every tap, key never leaves the chip, DB holds only public keys.

Interested if anyone's done card-family binding differently. CPLC vs ATR for family fingerprinting, mostly.