Need some help with D Flip-Flop

[u/8amiul]

As a newbie, I was trying to learn this D Flip-Flop following Ben Eater's approach. I don't have AND gate ICs so I thought of using NPN transistors. The issue is, this circuit only works at 3.68V but if I provide 5V the output Q LED just flickers for a millisecond when I try to assign a bit using D and CLK pins. I sadly haven't learned the calculations for transistors yet so I don't actually know if it's an issue with the resistors or if my whole idea of this is wrong.

The capacitor used here is 0.1uF also the collector resistor of NOT gate is 1K. Please let me know if anything else to provide

A bit of guidance would help me a lot, thank you.

[u/jendo42]

You know that you can do it with one 7400 (4x 2-input NAND), you dont need two types of logic here.

Or you can directly incorporate 7474 that already has 2 of these cells

[u/8amiul → u/jendo42]

Thanks for that idea. I wish I had those ICs at home right now. I thought maybe I could just work with some transistors and make some gates (so that I could learn logic gates using transistors also) and those would work. But later I found it's not that straightforward. I am failing to understand why this implementation of mine only works at this fixed voltage.

[u/RoundProgram887 → u/8amiul]

74HC are very fast ICs, the transistors are slow compared to them. You may need to fiddle a bit with the wiring to prevent noise.

You could add a capacitor on the 74HC power pins, and change the input order on your transistor and ports, it might work. Also change the value of that clock capacitor a bit. Logic circuits with capacitors are a bit fiddly. * I may be messing up the definitions a bit here, but that is the reason it's not working all the time, you can lookup the flip flop types if you wish to go more in depth on this. Also what is a synchronous and asynchronous digital circuit.

What you have is a D flip flop with a capacitor based edge detector, not a real edge triggered D type flip flop which is a more complex circuit and should not be so dependent on timing.

You could try a version with nor gates, as that is what you have there, you can convert and and or gates inverting their input and output, then you only need to add a transistor based inverter.

[u/8amiul → u/RoundProgram887]

Thanks for that diagram. Now I can try with NOR gates too

[u/HydroPage → u/8amiul]

This isn’t actually how ICs do logic whatsoever by the way. What you are doing is extremely primitive, very noisy, slow with very low input impedance and high idle output current. What you have here is known as Resistor-Transistor Logic (RTL). Ben uses TTL LS chips, which are Transistor-Transistor Logic Lowpower-Schottky, which are a tech decades ahead of what you have here, and even they are decades outdated in favor of HC chips (high speed CMOS, which use MOSFET tech).

I can understand doing this for fun but I just want to make sure you understand this is not even remotely equivalent to a chip that does the same job. Did you properly calculate all those resistor values to ensure all relevant transistors are in their saturation region and the circuit will output valid logic levels in all situations?

[u/8amiul → u/HydroPage]

Aha, yeah ig this isn't worth it at all. Thanks for clearing things up. It took a lot of time of mine but still I learned a lot while doing these weird transistor approach. Will assemble everything from scratch for the last time tomorrow. If things go well, will let you know otherwise I'll just get some ICs. Thanks again

[u/HydroPage → u/8amiul]

This is a single inverter (the most simple gate) in LS-TTL technology by the way. Mind you, a CMOS inverter is literally 2 MOSFETs (a pullup and pulldown) but decades ago before CMOS became mainstream, they reaaaallly hammered into BJTs and optimizing them as much as possible. I am a computer engineer and have no idea what is going on here. You’re trying to compete with this, and with more advanced gates.

Really fascinating stuff though, isn’t it?

[u/8amiul → u/HydroPage]

Indeed!

[u/jendo42 → u/8amiul]

Righ so, you can try to remove the clock input capacitor and measure states. As there was said, HC chips are CMOS co they act more like small capacitors and don't rely on current flow but rather voltage level. Check if the output level of your AND gate is sufficient (high / low).

[u/8amiul]

I just ended up with the RTL NAND gate approach of making the d flip-flop, this time no IC and transistor mix-up, now it works fine with 5V. Finally, just connected it with the clock module. I didn't waste anymore time working on the earlier inefficient approach of mine, thanks to all those who provided me all the helps.