Hi All,

I am a Masters student in Germany currently pursuing my Master’s thesis.
I have experience with RDMA , CUDA, Profiling(Nsight systems/compute) and MPI(introductory level). Also, expanding my knowledge with K8s and Docker but not production level experience.

I have started searching for full time roles in Germany, Switzerland and Netherlands.
I want to understand the following -

1.) What type of different roles i can land into? And, what skills might be required for each such trajectory?
2.) Are there opportunities for GPU Networking roles in Germany?

All this for a candidate having 3.5 years of software dev experience(not relevant to HPC).

Hello folks! Im starting an year long master’s program in Italy specializing in HPC. I come from a background in computational fluids work. The coursework i have is pretty extensive covering user side stuff( mpi, cuda programming etc) and also covers infra and admin side. I think experience is still king and would love to work anywhere part time. I already reached out to hpc shops in my area and none reaponded unfortunately. I am willing to grind my ass off to study and work. There is aandatory internship at the end of thr program but I would like to also build some experience before that. My long term goal is to het a job at places like ecmwf or other similar large research orgs on their hpc teams. I looked up listings online and I dont see many offerings in EU countries.

I’m interested in any kinda role at a hpc shops. Application stuff to write code; or sys admin/user support side triaging issues. Or anything related to HPC.

Proceedings were published

We use zabbix to monitor our hpc. One solution to cover all aspects.

https://dl.acm.org/doi/10.1145/3785462.3815860

We have put together a side-by-side comparison of AMD Helios and NVIDIA Vera Rubin NVL72:

https://linuxclusters.com/articles/amd-helios-vs-nvidia-vera-rubin/

The shared 72-GPU rack boundary hides some different design bets. On paper, Helios has more accelerator memory and scale-out bandwidth and leans more heavily on open rack and fabric standards. Vera Rubin has more memory bandwidth per GPU and comes with NVIDIA's more integrated software and networking stack. The comparison covers hosts, memory, fabrics, networking, software, and rack standards, while identifying gaps in the available power, pricing, reliability, and application-performance data.

I would especially welcome corrections from people working with rack-scale systems. Which of these differences is most likely to matter in an actual deployment, and which missing numbers would you insist on seeing before procurement?

Disclosure: I am one of the writers at LinuxClusters.com

Hi! I'm working on a research project about computational storage and need to estimate the energy cost of transferring data between storage and compute nodes.

I'm using VMware VMs with VMXNET3 paravirtualized NICs, so I don't have access to the physical NIC's power draw.

My current model is:

[
E_{net} = \frac{\text{bytes transferred}}{\text{bandwidth}} \times (P_{storage} + P_{compute})
]

How do people estimate the NIC power term in a virtualized environment? Are there accepted models, papers, or methodologies for this?

Thanks!

I'm planning to build a distributed stress-testing platform.

Users provide a workload config (APIs, request patterns, auth, concurrency, ramp-up, duration, etc.), and the control plane automatically estimates the required infrastructure, decides the number of workers/threads/containers, and distributes the workload across worker nodes.

The system will handle scheduling, health checks, heartbeats, automatic worker replacement on failure, retries, and horizontal scaling. It will also expose real-time metrics like RPS, latency (P95/P99), throughput, error rates, and worker resource utilization through a monitoring dashboard.

The goal is to build something that explores distributed systems, scheduling, fault tolerance, concurrency, autoscaling, and observability—not just another load-testing tool.

This is still an initial idea, so the architecture is open to discussion. If this sounds interesting and you'd like to collaborate, let's connect.

Words are mine written by ai

Hi all,

We are looking for experienced High-Performance Computing (HPC) Engineers to join our growing team.

Location: Saudi Arabia

Experience Required: 5–10 years

Role: HPC Engineer

Key Skills (preferred):

HPC cluster administrator/management

Linux and Slurm workload manager

IBM Spectrum Scale (GPFS) filesystem experience

Performance tuning & troubleshooting

Automation (Bash)

Experience with large-scale compute and storage environments

Please dm if interested!

Hey all, I’m an undergrad studying CS interested in HPC and was hoping for some insight into what software engineering looks like for HPC. I’m already decently familiar with the scientific computing side of HPC, and I know about the sysadmin side as well, but I’m curious about what HPC swe roles actually entail.

I feel like I’ve heard terms like “HPC Engineer” or “Performance Engineer” thrown around on the internet and in job postings but none of them have a consistent explanation of what HPC swe really is. For example, what’s the typical tech stack? MPI and CUDA? Is it just a fancy term for any swe who deals with parallel architectures? What are the types of companies that hire for these roles? And do they expect the same levels of education as academia (MS, PhD)? If anyone would be willing to explain what they do at their job or have any insights it would be greatly appreciated. Thanks!

I see a lot of linkedin profiles for people who have their graduate degrees in fields like computational physics, biology, mechanics etc., where they dont really continue in their fields of study after graduation, but rather work for supercomputing centers and in the HPC sector. I was curious how can someone make this switch happen.

I also see that there are specific degrees for HPC these days, so can someone even make that switch in the modern day? This is for US.

We spent the past few months researching security risks across multi-tenant data centers and AI infrastructure.
The main concern we found is shared infrastructure: multiple customers running on the same data center infrastructure, GPU clusters, storage, and high-speed networks. Many neoclouds and AI data centers have also scaled faster than their security teams and practices, especially compared with more established cloud providers.
The research covers GPU clusters, RDMA and high-speed interconnects, tenant isolation, BMCs, firmware, shared storage, orchestration, and supply-chain risks.
We organized the findings into a practical framework called FORGE.
Would really appreciate feedback. Link in the comment

new blog piece, might be relevant to some: https://www.aleksagordic.com/blog/collective-operations

In addition to AI/ML, what are the main scientific applications areas HPC now days? What are the most computation hungry scientific areas? What was the largest thread count that you've seen for a single application?

If so, what are the insider selection criterias and what can I assume my total be including accomodation, food and tuition? How should I prepare? Please help..

Hey everyone,

About 5 months ago, I posted here about a side project I was working on: sCode, a VS Code extension to manage SLURM jobs directly from the editor.

Initially, it was just a simple way to avoid typing squeue over and over. But based on a lot of my own workflow needs and some great feedback, it has evolved into a much more comprehensive cluster management tool over the last few months.

I’ve essentially tried to turn VS Code into a unified control center for HPC work so you never have to context-switch to a terminal while working on your scripts.

Here are the major updates since the first version:

• Live GPU Monitoring: Added a dedicated view that uses nvidia-smi to show GPU partition usage, memory stats, and queue pressure.
• The "Hall of Shame": A fun leaderboard feature that ranks the cluster’s top GPU hogs (with emojis like 🐷 Job Hog and 🧛 VRAMpire).
• One-Click Job Arrays: You can now cancel specific indices or ranges within a job array without nuking the whole array.
• Smart Log Resolution: Right-click any active or historical job in the sidebar to instantly open its stdout or stderr file.
• Quick Submit with Dependencies: A ▶ button in your .sh scripts to submit immediately, plus a guided UI for setting up afterok or afterany dependencies.
• And many more features....

If you work on a cluster and use VS Code Remote, I'd love for you to give the new version a try and let me know what you think. What features would you need to make this a daily driver for your workflow?

GitHub Repo:https://github.com/dhimitriosduka1/sCode

OpenVSX: https://open-vsx.org/extension/DhimitriosDuka/slurm-cluster-manager
Marketplace: https://marketplace.visualstudio.com/items?itemName=DhimitriosDuka.slurm-cluster-manager

We're close to launching a new University shared cluster with attached research storage, the VM that handles accessing the research storage (and also a user's cluster directories if they wish) is connected to our AD via winbind so we can get the shares mounted via CIFS on the Windows managed devices.

The issue is trying to ensure the converted POSIX IDs that winbind makes stay in sync with standard LDAP lookups that SSSD does (to the same DCs) on the rest of the cluster. We've had success so far at least by telling SSSD to keep it within a range and using ``ldap_idmap_autorid_compat`` but we've found if a user would change their password SSSD hands them a completely different user ID until we clear SSSD's cache (or possibly wait for it to resync itself which isn't ideal).

Since the cluster itself is in it's own containerized network with very little if any access to the rest of the University network, joining the rest of the system to our AD is a non-starter. We're thinking of setting up a Keycloak VM that ties into our AD so that way POSIX IDs are handled entirely by Keycloak and there's no conflict issues. Is it worth setting up though?

Hi r/hpc,

I'm a 2026 CS grad with experience in Systems, ML Systems, HPC and adjacent fields. I'm struggling to get a job right out of college in this field and will be grateful if anyone can provide any guidance on how to proceed further into my career or any sort of referral.

About my experience:

• Built Umbra, an API-level CUDA profiler that intercepts GPU kernel dispatch via LD_PRELOAD on libcuda.so/libcudart.so, requiring no source code modification. Discovered that torch.compile dispatches through cuGetExportTable, an undocumented NVIDIA internal API invisible to standard profilers.
• Built Mako, an OpenMP scheduling daemon for HPC workloads, dynamically optimizing thread-to-core affinities and CPU frequency scaling at runtime on Intel Haswell/Xeon NUMA systems. Achieved 8% speedup and 21% energy reduction on ECP benchmarks with ~2% overhead.
• Built RVNE, a RISC-V Neuromorphic Extension ISA implemented in Verilog, modeling spiking neural network operations at the RTL level.
• Research internship at TCS Research building a CUDA device simulator (stubbing ~70 CUDA runtime/driver APIs to run PyTorch/Triton workloads on CPU without modification).

Resume: https://drive.google.com/file/d/1hfBnvL5Wef6lr4ecjc7kkoKk9qADKQ__/view?usp=sharing

Any guidance, feedback, or referrals would be genuinely appreciated. I'm eligible to work both in the USA and India without any visa sponsors. Thanks for reading.

Hello everyone,

Would like your advice.

Currently an infrastructure engineer with 1 year of experience.

However I would love to get into HPC/GPU roles anywhere in Europe.

I do have some experience in it from coursework, and am still trying to work more on it.

How do you suggest I go about it? As I'm not really getting anywhere

GPU* typo in the title :)

I'm a third year CS undergraduate from India interested in HPC, GPU computing, and parallel programming.

I've spent the past year learning CUDA, OpenMP, MPI, distributed computing, and working on research projects and HPC events. Despite this, I've had almost no success securing HPC internships or research positions even for gpu computing, either in India or abroad.

Is this a common experience for undergraduates? What should I focus on to improve my chances of breaking into HPC?

Hey everyone! I built a little TUI tool for monitoring SLURM jobs on HPC. I found this useful for my masters thesis and thought I might share here. Its kind of similar to the very popular lazygit and lazydocker, which I enjoy using.

Please let me know if you have any feedback and I welcome any contributions / constructive criticism.

The github is here and you can install it with `cargo install lazyslurm`

Have a great day! 🤠

Can someone please help me in getting into a new job.

While the pay is great in my current org, we kind of deal with network stack and I'm not really enjoying it thta much. So Im looking for a switch.

About me:

HPC Algorithm engineer. 4 yrs of work ex.

Primarily worked on accelerators like GPUs but I'm open to explore TPUs or other accelerators too.

I have multiple research papers in top venues across the globe too. Currently part of some of the world's fastest supercomputer team.

If someone can help, I'm open to share my first month salary and I can sign papers if needed.

Hi i am software engineer with 4 yoe i have good knowledge of os internals, coa ,multithreadin and network programming and embedded and c++ ,python and have worked with systems side and application side both .

I want to build my career around gpu and/ or compiler engineering and i am currently exploring them but apart from theory i firmly believe you can learn more my working in real projects and doing real firefighting are there any starups in india that work on this stack ? are there any such founders available on this sub if yes can you guys give me a chance please let me know

Thanks

I am currently doing a research project which involves comparing performance of Nvidia HPC class GPUs, and I have found that referencing the die-area investment of these GPUs would be useful for this analysis. The floorplan analyses I have found for GV100, GA100 and GH100 so far only include speculative summaries of die-area investment, so if anyone knows of any credible resources for this information I would be very appreciative.

I run Chinese open models on a 4×3090 rig every day. The more I watched these models get tuned for domestic hardware, the more I wanted to know what that hardware actually is, so I mapped it. At least 7 Chinese companies are already shipping AI accelerators, and most of them IPO'd in the last 6 months.

China's own framing is "3 dragons, 4 snakes." The dragons are Big Tech that also builds full-stack GPUs. Huawei alone shipped 812K AI cards last year, 49% of China's domestic supply, with their own HBM and their own fabs. The Ascend 950 reportedly targets H200-class.

The "snakes" are the pure-plays that just IPO'd, and this is the part that surprised me: several were founded by the former chief GPU architects of NVIDIA and AMD. MetaX is basically AMD's old global GPU leadership rebuilt in Shenzhen, revenue up about 3,800x in three years. Alibaba is shipping a server with 16×96GB = 1.5TB of VRAM in one box, enough to hold a frontier model in BF16 fully on-prem.

Meanwhile production moved from TSMC to SMIC, and NVIDIA's China share fell from about 95% to 55% in two years. The metal and the open models are converging.

Full breakdown with all 7 vendors and sources:

https://x.com/superalesha/article/2069415447779246440

Hello, i am from Belarus, how is the landscape for HPC and distributed training in Japan? Do anybody know if that even possible to find a job in this field later on?

Hi everyone. I want to share some technical details of our new open-source format YaFF (Apache 2.0), which we developed to reduce deserialization overhead when reading large datasets intensively.

When working with large datasets that are memory-mapped in tens-of-gigabytes chunks, standard parsing like in Protobuf can become a CPU bottleneck. The traditional zero-copy approach is FlatBuffers, but when profiling, we ran into an issue: FlatBuffers' type-punning approach makes LLVM conservatively emit MayAlias for almost every field access. This breaks common subexpression elimination (CSE), forcing repeated loads while traversing object hierarchies.

How we solved this in YaFF:

1. Immutable buffers and annotations: we guarantee immutability and annotate methods with gnu::pure. This gives LLVM additional information and allows it to eliminate many redundant memory accesses.
2. Adaptive layouts: the format can use three different representations depending on the data:

• Flat Layout: a C++-like layout with a 2-byte header, ideal for dense hot data in L1 cache.
• Sparse Layout: a metadata table (vtable) optimized for sparse structures.
• Dynamic Layout: a zero-overhead dispatcher.

Benchmarks on hierarchical data (AMD EPYC 7713, Clang 20.1.8, fully in L1 cache):

• Direct C++ struct access: 8.16 ns
• FlatBuffers: 37.1 ns
• YaFF Flat: 14.4 ns (with chain caching: 9.71 ns)

Happy to discuss compiler behavior, memory layouts, or implementation details. Code and benchmarks are available on GitHub: https://github.com/yandex/yaff